Comparing with the traditional technique, the Gate driver On Array (GOA) technology not only saves the cost but also realizes the symmetrical design on both sides of a display panel, without the bonding area and the wiring area (e.g., a fanout area) of a chip, and is thus in favor of realizing the design of a narrow bezel. At the same time, because the GOA technology may eliminate the chip bonding process in the line direction, it is greatly helpful to the overall production capacity and the improvement of yield.
In the GOA design, a first node which controls the signal output and a second node which controls signal resetting are arranged in a shift register. The second node is reset periodically by a clock signal via thin film transistors (TFT) connected in a diode form. Therefore, the TFT will be constantly in an on-off switching state under the action of the clock signal, and thus tends to result in a large threshold voltage drift, thereby affecting the electric potential of the second node and resulting in an abnormal output signal of this stage. The abnormal signal will be passed down via the cascading shift registers, resulting in a wide range of display disorder.
In order to solve this problem, voltage division or the like may be introduced to reduce the gate voltage of the TFT, to alleviate the threshold voltage drift and enhance the stability of the shift registers. However, the TFT which is configured to reduce the gate voltage is also connected with the clock signal, so there is still a problem of the threshold voltage drift, and as the long-term effect, the output signal will still be abnormal. That is, the above means may only alleviate the signal distortion to a certain extent but cannot solve the problem of the abnormal output signal.